1. Field of the Invention
This invention relates to a control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system.
2. Description of the Related Art
A flash memory is available as one of the memories used with small information devices, machines, etc. The flash memory has the following four advantages as a promising memory replacing a hard disk:
1. Data is retained if in a flash memory even if power is turned off (data in DRAM is lost when power is turned off). PA1 2. Reading of data of a flash memory is relatively fast as read compared with hard disk. PA1 3. A flash memory semiconductor device, has good resistance to vibration as compared with that of a hard disk. PA1 4. A flash memory is less expensive as compared with a SRAM. PA1 1. When data is written, the write area contents must have been erased. PA1 2. Erasure is made in chip units or block units of a given size. PA1 3. It takes time for a write operation to be implemented for reasons 1 and 2. PA1 4. Since elements are degraded by repeating a write, operation the write count is limited.
However, the flash memory has the following disadvantages:
FIG. 97 is a schematic diagram of a flash memory containing 1024 blocks each consisting of 512 bytes (524288 bytes in total). In FIG. 97, numeral 4110 denotes one block in the flash memory and numeral 4111 denotes a 1-byte data retention section in the block 4110, which will be hereinafter referred to as a cell. Numeral 4105 is a control circuit. When a read access is made to the flash memory, data is read from the cell determined by address signal A0-A8, a buffer 4121, and a decoder 4122 in the block determined by address signal A9-A18, a buffer 4131 and a decoder 4132 and is output via a register 4141 to I/O0-I/O7. Numeral 4123 is a control signal of the buffer 4121 and the decoder 4122. Numeral 4133 is a control signal of the buffer 4131 and the decoder 4132. Numeral 4142 is a control signal of the register 4141. On the other hand, when a write access is made to the flash memory in FIG. 97, the contents of the block determined by the address signal A9-A18 , the buffer 4131, and the decoder 4132 are erased and input data from I/O0-I/O7 is written via the register 4141 into the cell determined by the address signal A0-A8, the buffer 4121, and the decoder 4122. Numeral 401 is a control signal of the controller 4105.
The limit of the write count mentioned above will introduce a serious problem with the use of the flash memory as storage media of a semiconductor disk. For example, data is written into areas such as a directory and FAT (file allocation table) on a disk more frequently than other areas, that is, data is frequently written into only specific blocks of the flash memory allocated to the directory and FAT and there is a good chance that the write count limit of the flash memory will be exceeded in the specific blocks faster than in other blocks. If the write count limit is exceeded, the elements are degraded and it may be impossible to carry out a normal read or write. If a directory or FAT on a disk is destroyed, the entire disk cannot be read. Therefore, malfunction only in specific blocks makes the entire semiconductor disk unusable, leading to poor efficiency.
A flash EEPROM (electrically erasable and programmable read only memory) system is described in Japanese Patent Laid-Open No. Hei 2-292798 as the related art of a file storage using a flash memory as storage media.
The related art provides a corrective action when a defective cell occurs in the flash memory. For example, the related art proposes that alternate cells are provided and that error correction control is performed so as to correct data disordered due to occurrence of a defective cell to normal data, whereby the write count limit as the disadvantage of the flash memory is overcome and the system life is extended. Also, the system is provided with a write cache memory and write back into the flash memory is executed based on the elapsed time from the last write into the cache memory. Data frequently rewritten is rewritten into the cache memory rather than the flash memory to reduce the operation of the flash memory in order to extend the over all system life.
In the error correction control, an error correction code is given for each sector (512 bytes), which is a storage unit of the flash memory conforming to a storage unit of the magnetic disk apparatus and when a data error occurs due to an element failure, it is detected and corrected based on the error correction code, thereby substantially increasing the number of times a write operation can be made. In the time monitor control of file rewrite, specifically, the time until a once written file is next rewritten is monitored and if the file is not the longest unrewritten file, the data in the file is stored in a volatile buffer (cache memory) in order to reduce the substantial write count of the flash memory for frequently rewritten files such as a directory and FAT.
The idea is intended to ensure the practical life of a storage using the flash memory.
However, to use the error correction codes, it requires much time and enormous throughput to generate the codes and detect and correct errors, lowering performance and complicating circuitry.
Use of the volatile buffer memory (cache memory) is not intended for covering slow rewrite which is another disadvantage of the flash memory. Frequently rewritten files are stored in the cache memory, but a large file cannot be stored in the cache memory.
For example, a large file first written is written directly into a flash memory having slow write speed rather than a cache memory, thus a write access becomes slow. For large-capacity continuous data that can be accessed at high speed on a magnetic disk unit, the file system is very inferior to the magnetic disk unit in access performance.
In Japanese Patent Laid-Open No. Hei 5-204561 filed previously by the present applicant, to solve the problem, an alternate memory area is provided to prolong the semiconductor disk life. However, since the alternate memory area is previously allocated as a fixed area, once it runs out of space, additional alternate memory area becomes unavailable.
In addition, in Japanese Patent Laid-Open No. Hei 2-292798, data is transferred from the cache memory to the flash memory when extra space is required in the cache memory. However, when extra space is required, a request to store data may occur within the system, thus a write into the flash memory which is slow in rewriting would lower system performance.
As described above, control is intended to write frequently written data only into the cache memory, thus not all write data can be written at high speed. When a defective cell occurs on one sector, it takes time to perform the corresponding proper action.
As a result, the data transfer time is prolonged and data transfer is delayed. Particularly, processing using the error correction code becomes complicated. The cache system in Japanese Patent Laid-Open No. Hei 2-292798 is provided to extend the system life. Although the technique about handling of cache data at data write is disclosed, no techniques about transfer of read data from the host which is an external system are disclosed. Therefore, the related art does not provide means accessible at high speed.
The main purpose of the related art is considered to replace magnetic disk units. The related art assumes an access in sector units via an external I/O bus provided for the system to transfer data to and from the external devices. However, it does not consider a random access from the CPU when the flash memory is used as the main memory, that is, direct data transfer in small units of several bytes, etc. The alternate cell method and error correction code processing are designed to transfer data in sector units; data cannot be transferred in byte or word units.
On the other hand, high-performance personal computers, etc., often use a DRAM-SRAM cache system as means for shortening the read or write time. Generally, the cache memory is located between the CPU and storage taking time to access for serving as a buffer memory. When the CPU reads the storage, the read address and data are stored in the cache memory. When the CPU then reads the same read address of the storage, the data corresponding to the address is obtained from the cache memory, thereby shortening the access time. The two systems of cache memory are known: Write through and copy back. The write through system is a system which rewrites the storage as well as the cache memory at the same time in response to a write request into a storage. On the other hand, the copy back system is a system which is responsive to a write request into a storage for rewriting only the cache memory without rewriting the storage which requires a lot of processing time and is intended to shorten the access time.
The cache memory system generally used with information processing systems such as personal computers at present includes the main memory of DRAM (dynamic random access memory) and a cache memory of SRAM (static random access memory) to cover the weak point that the DRAM access operation cannot keep up with the CPU operation speed. Accessed addresses are allocated to the SRAM and the DRAM accessed at slow speed is used to back up data as if the SRAM accessed at fast speed were the main memory when viewed from the CPU. In this technique, the SRAM access speed is several times as fast as the DRAM access speed, and although it i less than ten times as fast. Thus, when a write access is made to an address not allocated to the cache memory, namely, when write miss occurs, the recovery time is not so great. If the flash memory is adopted as the main memory, the flash memory has the rewrite time 1000 to 100000 times longer than the DRAM, and the recovery time at write miss becomes very great, lowering system performance. Therefore, this point must be considered when implementing a system.
To reduce flash memory chip costs, those skilled in the art focus attention on a cell structure for reducing the flash memory chip area. For example, a flash memory having a so-called NAND structure is adopted. In this structure, a line access rather than a random access is made and data is input/output in series in line units. For the future flash memory, it is considered that the line access system intended for high integration of memory will become the main stream. In addition, development of a memory adopting an access system similar to the line access system is pursued. Even if a memory of such a structure is used, it will become an important technology with regard to making random accesses at high speed. This point is not considered in the related art including Japanese Patent Laid-Open No. Hei 2-292798 discussed above.
Whether the main memory is volatile or nonvolatile makes a great system difference.
For example, when the main memory is volatile, if the system power is turned off with only the cache memory rewritten, data stored in both the main memory and the cache memory is cleared, introducing no problem. However, when the main memory is nonvolatile, if the power is turned off with the most recent data stored only in the cache memory, in fact the data just entered and still being considered by the user can disappear from the cache memory.
If the main memory of an information processing system is volatile, it is common practice to provide an auxiliary storage for saving file data. However, if the main memory system is nonvolatile, no auxiliary storage is required. (The main memory serves as a data save area.) This point is one of the merits of the system provided with the nonvolatile main memory, but it introduces a problem. For example, information processing systems may career out of control due to a program error or operator mistake. When this fault occurs, if the main memory is volatile, it is possible to reset the hardware or, as a last resort, temporarily turn off the power and restart the system, thereby clearing the main memory contents and again loading data into the main memory from the auxiliary storage for restoring the system to the normal state. However, if the main memory is nonvolatile, when the system careers out of control and data stored in the main memory is destroyed, correct data is lost and it is difficult to restore the system to the normal state.
Therefore, the information processing systems having a nonvolatile main memory must be provided with a corrective system for crashing of the processing system.